1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming an epitaxial (epi) block layer to increase uniformity during epi growth in a fin field effect transistor (FinFET) device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
The fin-shaped field effect transistor (FinFET) is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
FinFET architecture typically takes advantage of self-aligned process steps to produce narrow features that are much smaller than the wavelength of light that is generally used to pattern devices on a silicon wafer. It is possible to create very thin fins (e.g., 20 nm in width or less) on the surface of a silicon wafer using selective-etching processes. The fin is used to form the raised channel. The gate is then deposited so that it wraps around the fin to form a trigate structure. As the channel is extremely thin, the gate typically has much greater control over the carriers within it. However, when the device is switched on, the gate shape limits the current through the gate to a low level. Consequently, multiple fins may be used in parallel to provide higher drive strengths.
In one prior art approach, as shown in FIG. 1, device 10 includes a dummy gate 12 covering an isolation trench oxide 14 between a pair of neighboring FinFETs 16A-B. Device 10 further comprises an epitaxial source 18 and drain 20 formed within a substrate 22, and spacers 24 formed along finFETs 16A-B and dummy gate 12. However, patterning isolation trench 14 to reach the small critical dimensions (CD) required is difficult with conventional lithography and etch techniques available. Device 10 suffers from leakage between the S/D through the dummy gate 12.
Furthermore, as shown in FIG. 2, during actual formation, isolation trench 14 is larger than dummy gate 12, and the epitaxy (epi) of source 18 and drain 20 grows non-ideally, which results in asymmetric growth without ideal facets, as well as insufficient tensile stress applied to the transistor channel. This is especially problematic when trying to land source and drain contacts on the epi of source 18 and drain 20. In this case, the contact area will not be positioned as high as desired, which may result in current crowding issues. What's more, the structure of device 10 still provides a potential leakage path through dummy gate 12.